ARM Processor

The ARM processor is basically a RISC (Reduced Instruction Set Computer). The first ARM processor was developed at Acron Computers Limited, of Cambridge, England, between October 1983 and April 1985. ARM is the industry’s leading provider of 32-bit embedded RISC microprocessor. ARM offers a wide range of processor cores. These are based on a common architecture and delivering high performance together with lower power consumption and lower system cost.

The ARM processor range provides solutions for:

• Real systems for networking applications, mass storage and automotive, industrial applications.
• Secure applications including smart cards and SIM cards and payment terminals.

ARM processor uses a RISC architecture. It contains a large number of registers. The instruction set contains separate load and store instructions for transferring data between the register bank and external memeory. When the data is to be operated, it is stored in the register and then processed. The memory accesses are separated from data processing. So we can use data items stored in registers multiple times without multiple memory accesses. This is advantageous since memory accesses are costly.

ARM processor executes most of the data processing instructions in a single cycle. However many other instructions need multiple clock cycles for their execution. More than one clock cycle becomes the requirement even for a simple load and the store instruction.

The ARM processor can be operated in different modes. The processor mode decides which registers are active and the access rights to the cpsr register itself. The modes can be classified in two groups, privileged and non-privileged.

Privileged mode: This mode allows full read write access to the cpsr

Non privileged mode: This mode only allows read access to the control field in the cpsr. However it allows read-write access to the condition flags.

The ARM processor can be operated in seven different modes as listed below:

Six Privileged modes:

a. abort – when an attempt to access memeory is failed, the processor enters an abort mode.

b. fast interrupt request & c. interrupt request – These two modes correspond to the two interrupt levels available on the ARM processor.

d. supervisor – After reset, the processor enters supervisor mode. An operating system kernel generally operates in this mode.

e. system – This is the special version of user mode. This mode allows full read-write access to the cpsr.

f. undefined – When an undefined instruction appears the processor enters this mode.

One nonprivileged mode:

a. User – Most application programs execute in user mode. While the processor is in User mode, the program being executed is unable to access some protected system resources or to change mode, other than by causing an exception to occur. This allows a suitably written operating system to control the use of system resources.

ARM processor supports five types of exception and a privileged processing mode for each type.

The five types of exceptions are:

• Fast interrupt
• Normal interrupt
• Memory aborts which can be used to implement memory protection or virtual memory
• Attempted execution of an undefined instruction
• Software interrupt (SWI) instructions which can be used to make a call to an operating system.

In case of an exception some standard registers are replaced with registers specific to the exception mode. r13 and r14 are the replacement banked registers for all exception modes. The fast interrupt mode has more registers for fast interrupt processing.

r14 holds the return address for exception processing when an exception handler is entered. It is used to return after the exception has completed processing and to address the instruction that caused the exception.

Register 13 is banked across each exception mode in order to provide each exception handler with a private stack pointer. The sixth privileged processing mode, system mode, uses the user mode registers to run tasks that require privileged access to memory, without limitations on which exceptions can occur during the task.

- Ankita Ashesh

Tags: acron computers, arm, arm processor, arm processor architecture, arm processors, arm risc processor, processing mode, processor, reduced instruction set computer, risc

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